LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
--USE ieee.std_logic_arith.all;
--USE ieee.std_logic_unsigned.ALL;
USE WORK.p_stop_watch.ALL;

ENTITY stop_watch IS
	PORT ( 	clk: IN STD_LOGIC;
			stop: IN STD_LOGIC;
			reg: OUT INTEGER);
END stop_watch ;

ARCHITECTURE stop_watch OF stop_watch IS
	signal s_i: INTEGER;
BEGIN
	U1: counter PORT MAP(clk, stop, s_i);
	U2: regis PORT MAP(s_i, stop, reg);
END stop_watch;